The wide use of computer technology over the past few decades has led to a variety of architectures for transferring information between a computer system's central processing unit (CPU) and its input/output (I/O) components, such as floppy and hard disk drives, monitors, user-input devices, and other peripheral devices in a computing system. One more recently-developed architecture uses a bus interface known as a peripheral component interface (PCI) bus interface. The structure of a computer system utilizing PCI buses and PCI bus interfacing technologies is illustrated in the context of FIG. 1.
In the system of FIG. 1, a personal computing system, or personal computer (PC), having a CPU 10 such as an 80486 or Pentium-type microprocessor device, is connected to memory 12, such as a random access memory (RAM), via a host bus 14. A host bridge 16 connects the host bus to a PCI bus, labeled PCI bus-0 18. PCI bus-0 18 is connected to a first PCI device 20, and is optionally coupled to other PCI devices represented by dashed block 22. PCI bus-0 18 is connected, via PCI bridge-1 24, to PCI bus-1 26. PCI bus-1 26 may be connected to PCI option slots 28 into which a first PCI option card 30 is inserted. PCI option card 30 contains a second PCI to PCI bridge 32 which allows interaction between PCI bus-1 26 and PCI bus-2 34. PCI bus-2 34 supports other PCI devices 36, 38, as well as additional PCI devices represented by dashed block 39. Additional PCI option cards 40 may also be inserted in the PCI option slots 28 for connecting additional PCI devices to the CPU 10.
The host bus 14, which couples the CPU 10 to the memory 12, operates at relatively high clock speeds, which provides for a relatively high information transfer rate between the CPU 10 and the memory 12. The host bridge 16, connecting other devices to the CPU 10, operates at relatively lower speeds. The PCI to PCI bridge-1 24 permits the optional extension of the PCI network, so that additional PCI devices can be connected to the CPU 10. The PCI to PCI bridge-1 24 is required to transfer data according to PCI standards, including 32 or 64 bit data words at 33 MHz or 66 MHz clock rates respectively. To maintain high data throughput, it is important that the PCI to PCI bridge-1 24 device minimizes delays caused by the accumulation of queued commands. The ability to provide a variable sequence of command responses, with respect to the original command order, is therefore desirable.
As described in the PCI to PCI Bridge Architecture Specification, Revision 1.0, Apr. 5, 1994, prepared by the PCI Special Interest Group, a PCI to PCI bridge must ordinarily maintain the coherency and the consistency of data that traverse the bridge. This includes data moving in either direction. Ordering rules exist for transactions that cross a PCI to PCI bridge.
Ordering generally refers to the relationship between a sequence of events on a particular bus. This sequence is independent of the transaction type, i.e., whether the transaction is a read or write. Since a bus bridge deals with two streams of events, it maintains ordering of both streams. This implies that when the bridge transfers events from one bus to the other, the relationship that existed on the initiating bus is maintained on the target bus. Ordering relationships are ordinarily established when an access completes on a bus, rather than when it is initiated. Therefore, an access that is terminated without transferring data has not occurred on the bus, and has no relationship with any other access. Accesses on different busses only have an ordering relationship established when a read traverses the bridge. Write transactions are ordered only with respect to other transactions on the same bus.
A prior art ordering sequence is described and illustrated in the PCI to PCI Bridge Architecture Specification prepared by the PCI Special Interest Group. There are two access sequences between a primary bus and a secondary bus across a PCI to PCI bridge. One access sequence is on the primary bus and one is on the secondary bus. For example, the primary bus access sequence may be a, b, c, d, e, f, g, h, i, and the secondary bus sequence may be 1, 2, 3, 4, 5, 6, 7, 8, 9. When the PCI to PCI bridge has been programmed to forward accesses from one bus to the other, the ordering of those accesses is maintained. In one example, the PCI to PCI bridge may forward accesses b, d, f, and h from the primary bus to the secondary bus, and the bridge forwards accesses, 1, 2, 5, 7, and 9 from the secondary bus to the primary bus. The resulting sequence on the primary bus would be a, b, 1, 2, c, d, e, f, 5, 7, g, h, i, j, 9, while the resulting sequence on the secondary bus would be b, 1, 2, 3, 4, d, f, 5, 6, 7, h, 8, 9. The access order does not change, regardless of which bus the access originates or is completed on.
"Posted" memory accesses may be allowed to move ahead of a previously initiated "non-posted" access. Write data is "posted" when the data is configured to be accepted immediately by the target device, and the target has accepted responsibility for the command. The target takes responsibility to complete the operation by accepting the posted write command, and responds to the initiator that the command will be completed at the target. The cycle is complete on the initiating side when the target responds that it will accept responsibility for the command. Analogously, a "non-posted" memory transaction is one where the action must be completed on the target side before the target will return a response indicating a completed command cycle. The initiator passes the data through the bridge, and initiates a command cycle on the target on the other side of the bridge. The target then completes the action directed by the command, and sends a response to the initiator. The initiator never relinquishes its responsibility for completing the cycle as in the posted memory transaction. Read commands are non-posted memory transactions, because they require the return of data to complete the cycle. An access order change may occur when an access that is "posted" by the bridge is allowed to pass a "non-posted" access.
Despite the ability of posted commands to pass non-posted commands, the response order of non-posted commands follows the order of the commands as issued. This includes the order of those commands which must be "retried", which occurs when the command is not successfully completed at the target bus. Data throughput is adversely affected by this sequencedependence, and it is therefore desirable to minimize the delays caused by the accumulation of queued, sequence-dependent commands.
Accordingly, there is a need for an arrangement for allowing sequence-independent command responses across a PCI bridge. The present invention is directed to a system and method for providing a variable sequence of command responses, thereby minimizing the accumulation of commands, by allowing command responses to occur in the order that they are completed, rather than in the order they are initiated. The present invention provides an arrangement which overcomes the aforementioned drawbacks, and offers other advantages over the prior art.